A computer system has a memory capacity of 4K × 8 bits. How many address lines are required on the address bus to identify every byte in this memory uniquely?
- (a)12 lines
- (b)8 lines
- (c)10 lines
- (d)16 lines
Answer
Why
Correct — A. 4K × 8 bits means 4K locations, each 8 bits (one byte) wide. The 8 is the data width and does not change the number of addresses.
4K = 4 × 1024 = 4096 locations
n address lines select 2ⁿ locations
2¹² = 4096 → n = 12
→ option (a)
Why the others are wrong
- (b)8 lines — 8 is the word width, the bits read at each address. Eight address lines reach 2⁸ = 256 locations, far short of 4096.
- (c)10 lines — 10 lines give 2¹⁰ = 1024 locations, which is 1K. That ignores the 4 in 4K: since 4 = 2², 4K needs 10 + 2 = 12 lines.
- (d)16 lines — 16 lines address 2¹⁶ = 65,536 locations, which is 64K. That suits a 64K memory, sixteen times larger than this one.
Concept
Each address line carries one bit of an address, so n lines can form 2ⁿ different addresses. To give every location its own address, 2ⁿ must reach the number of locations.
A memory written as words × width (here 4K × 8) has that many words of that many bits each. The number of words sets the address bus. The width sets the data bus, 8 bits here.
The stem asks about identifying every byte. Each location here is exactly 8 bits, so locations and bytes are the same count, 4096.
Key facts
- n address lines can address 2ⁿ locations.
- In memory sizes, 1K = 2¹⁰ = 1024.
- 4K = 2¹² = 4096, so a 4K memory needs 12 address lines.
- In a words × width memory, the width (here 8 bits) sets the data-bus width, not the address-bus width.
Study next
Common traps
- Answering 8 by reading the word width as the number of address lines.
- Treating K as 1000 instead of 1024, which makes the power of two look inexact.
The capacity is given as words × width, and one wrong option is the width itself. The register that holds a memory address, the MAR, is an option at 19 Jan 2026, 11:00 AM, Computer Knowledge Q.6.
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