EPFO APFC 2023 General Studies · Question 86 of 120

Correct — B, (b) MAR. MAR stands for memory address register, and its single job is to hold the address of the memory location that the processor is about to read from or write to. Its output drives the address bus, so whatever address is standing in the MAR is the address the memory will act on when the read or write control signal is asserted. That is exactly what the stem describes: the address of the next location in memory to be accessed. Watch it work through one instruction cycle. At the start of a fetch the address of the instruction to be fetched is copied from the program counter into the MAR; the memory is read; the word that comes back arrives in the memory buffer register; from there it is transferred into the instruction register for decoding; and the program counter is incremented so that it points at the following instruction. If the decoded instruction needs an operand from memory, the address of that operand is placed in the MAR in its turn and the same read is performed again. The MAR is therefore used more than once per instruction, and it is used for data addresses as well as for instruction addresses, which is why the stem's wording is 'the next location in the memory to be accessed' rather than 'the next instruction'. That distinction is the one point on which this item can be lost by knowing too much. The register that holds the address of the next instruction to be executed is the program counter, also called the instruction pointer, and a candidate who reads the stem as asking for it will look for a program counter among the options, not find one, and then guess. The program counter is not offered here. Among the four registers that are offered, only the MAR holds an address at all; the other three hold instructions or data.

• (a)IR — IR is the instruction register, and it holds the instruction currently being executed, not an address. Its contents arrive at the end of the fetch phase — the word read out of memory passes through the memory buffer register and is deposited here — and they stay for the decode and execute phases, so that the control unit can examine the operation code and work out what signals to raise. The confusion this option trades on is that an instruction usually contains an address inside it, in its operand field. But containing an address as part of an encoded instruction is not the same as being the register whose contents are presented to the memory. When that operand address is needed, it is extracted from the instruction register and loaded into the memory address register, which is where every address must stand before memory can be accessed.
• (c)MBR — MBR is the memory buffer register, called the memory data register in many texts, and it is the MAR's partner rather than its equivalent. Every transfer between the processor and main memory uses both: the MAR holds the address and drives the address bus, while the MBR holds the data and sits on the data bus. On a read, the word that comes back from the addressed location lands in the MBR; on a write, the word to be stored is placed in the MBR before the write signal is given. So the MBR does hold something that has just come from memory or is about to go to it, which is why it attracts a candidate reading quickly, but what it holds is the contents of a location and never the identity of one. The widths of the two registers reflect this division: the MAR is as wide as an address and the MBR as wide as a word.
• (d)DR — DR is a data register. The name is used loosely across textbooks — in some it is a general purpose register holding an operand on which the arithmetic and logic unit is about to work, and in others it is simply another name for the memory buffer register — but on every reading it is a register that holds data rather than an address, and that is enough to eliminate it here. The general point is worth carrying: the special-purpose registers of a processor divide into those that hold addresses, such as the memory address register, the program counter, the stack pointer and the index registers, and those that hold values, such as the accumulator, the data or buffer registers and the flag register. A question that asks which register holds an address has already excluded the whole of the second family.

A register is a small, very fast storage location inside the processor itself, at the top of the memory hierarchy above cache, main memory and secondary storage. A few registers are general purpose, but the ones examinations ask about are the special-purpose registers, each with a defined role in the instruction cycle. The program counter holds the address of the next instruction to be fetched and is incremented as each fetch completes, or reloaded when a branch is taken. The memory address register holds the address of the location the processor is about to read or write, and drives the address bus. The memory buffer register, also called the memory data register, holds the word being transferred to or from that location, and sits on the data bus. The instruction register holds the instruction currently being decoded and executed. The accumulator holds an operand or a result for the arithmetic and logic unit, and the flag or status register records conditions such as carry, zero, sign and overflow that the last operation produced. The instruction cycle strings them together in a fixed order: the program counter's contents move to the memory address register, memory is read into the memory buffer register, the word moves into the instruction register, the program counter is incremented, the control unit decodes the instruction and raises the signals that execute it, fetching any operand through the same address-and-buffer pair. Two widths follow from this arrangement and are often asked about directly: the number of bits in the memory address register fixes how many distinct locations can be addressed, and the width of the memory buffer register matches the word length of the machine.

The computers block of this paper mixes questions the candidate can reason out with questions that simply require the vocabulary, and this is one of the second kind. Its difficulty is not conceptual — anybody who knows what the four abbreviations expand to can answer it in a few seconds — but it is a good example of an item that is harder for a well-prepared candidate than for a moderately prepared one. The reason is the stem's phrasing. Anybody who has learnt the instruction cycle knows the sentence 'the register that holds the address of the next instruction' and attaches it firmly to the program counter, and this stem is close enough to that sentence to trigger the association while being about something else. It says 'the next location in the memory to be accessed', which covers an operand address just as much as an instruction address, and it is answered by the register that presents an address to memory in every case, the memory address register. The program counter is not among the options at all, and the absence of an expected option is a signal to reread the stem rather than to compromise. The preparation this rewards is to learn the abbreviations in their pairs and their sequence rather than as a list — program counter to memory address register, memory to memory buffer register, memory buffer register to instruction register — because a question about any one of them can then be answered by walking through the cycle.

• The memory address register holds the address of the memory location that is about to be read or written and drives the address bus. Every access to main memory, whether it fetches an instruction or an operand, presents its address through this register.
• The program counter, also called the instruction pointer, holds the address of the next instruction to be fetched and is incremented after each fetch or reloaded on a branch. It is the register the phrase 'address of the next instruction' belongs to, and it is not among this question's options.
• The memory buffer register, called the memory data register in many texts, holds the word being transferred to or from memory and sits on the data bus. It works as a pair with the memory address register: one carries the identity of the location and the other its contents.
• The instruction register holds the instruction currently being decoded and executed, having received it from the memory buffer register at the end of the fetch. The address inside its operand field must still be loaded into the memory address register before that operand can be read.
• The instruction cycle in order: program counter to memory address register, read memory, word into memory buffer register, word into instruction register, increment the program counter, decode, then execute, fetching any operand through the same address and buffer registers.
• The width of the memory address register fixes the size of the addressable memory, since an n-bit address can name two to the power n distinct locations, while the width of the memory buffer register matches the machine's word length.

• Reading the stem as 'the address of the next instruction' and looking for a program counter. The stem says the next location in memory to be accessed, which covers operands as well, and the program counter is not offered.
• Choosing the instruction register because an instruction contains an address in its operand field. Holding an encoded address inside an instruction is not the same as being the register that presents an address to memory.
• Confusing the memory buffer register with the memory address register. They are used together on every memory access, one for the address and one for the contents, and the abbreviations differ by a single letter.
• Treating the data register as a possible address holder. Registers divide into those that hold addresses and those that hold values, and a question asking for an address has already excluded the second family.
• Assuming a register is used only once per instruction. The memory address register is loaded again for every operand access, which is why its description is written in terms of locations rather than instructions.

Processor registers appear in this exam in three recurring forms. The first is the identification asked here: a one-line description of a role, with four register abbreviations as options, where the whole difficulty is in matching the description to the right member of the set. The second runs the instruction cycle explicitly and asks what happens at a named step — which register's contents move where during fetch, or which register receives the word read from memory. The third asks a consequence of a register's width: how much memory an address register of a given size can address, or what the word length of a machine implies. All three are covered by learning six registers with one sentence each and the order in which the cycle uses them. Expect the stem to be phrased in a way that resembles the description of a neighbouring register, and expect the most obvious candidate for a misread stem to be absent from the options, since that absence is the setter's way of forcing the stem to be read again.

No directly related past PYQ was found.

• practice — not a real PYQ

  During the fetch phase of an instruction cycle, the contents of which register are transferred into the memory address register so that the instruction can be read from memory?

  • (a)The instruction register
  • (b)The program counter
  • (c)The accumulator
  • (d)The status or flag register

  Answer(b) the program counter — it holds the address of the next instruction to be fetched, so a fetch begins by copying that address into the memory address register, from where it drives the address bus. The instruction register receives the instruction only after it has been read, the accumulator holds operands and results for the arithmetic and logic unit, and the flag register records conditions produced by the last operation.

• practice — not a real PYQ

  Which one of the following registers holds the instruction that is currently being decoded and executed by the control unit?

  • (a)The program counter
  • (b)The memory address register
  • (c)The instruction register
  • (d)The memory buffer register

  Answer(c) the instruction register — the fetched word is deposited there from the memory buffer register and stays while the control unit decodes the operation code and raises the signals that carry it out. The program counter holds the address of the next instruction, the memory address register the address of the location being accessed, and the memory buffer register the word in transit to or from memory.